UPD78F1502AGK-GAK-AX Datasheet, PDF (135/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 3 CPU ARCHITECTURE
3.4.8 Based indexed addressing
[Function]
Based indexed addressing uses the contents of a register pair specified with the instruction word as the base
address, and the content of the B register or C register similarly specified with the instruction word as offset address.
The sum of these values is used to specify the target address.
[Operand format]
Identifier
−
−
Description
[HL+B], [HL+C] (only the space from F0000H to FFFFFH is specifiable)
ES:[HL+B], ES:[HL+C] (higher 4-bit addresses are specified by the ES register)
Figure 3-34. Example of [HL+B], [HL+C]
OP code
FFFFFH
rp (HL)
Target memory
F0000H
r (B/C)
Memory
Figure 3-35. Example of ES:[HL+B], ES:[HL+C]
FFFFFH
OP code
ES
rp (HL)
Target memory
r (B/C)
Memory
00000H
R01UH0004EJ0501 Rev.5.01
119
Jun 20, 2011