UPD78F1502AGK-GAK-AX Datasheet, PDF (254/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 5 CLOCK GENERATOR
<3> Waiting for the stabilization of the subsystem clock oscillation
Wait for the oscillation stabilization time of the subsystem clock by software, using a timer function.
Caution The CMC register can be written only once after reset release, by an 8-bit memory manipulation
instruction.
Therefore, it is necessary to also set the value of the EXCLK and OSCSEL bits at the same time.
For EXCLK and OSCSEL bits, see 5.6.1 (1) Example of setting procedure when oscillating the X1
clock or 5.6.1 (2) Example of setting procedure when using the external main system clock.
(2) Example of setting procedure when using the subsystem clock as the CPU clock
<1> Setting subsystem clock oscillation^Note
(See 5.6.3 (1) Example of setting procedure when oscillating the subsystem clock.)
Note The setting of <1> is not necessary when while the subsystem clock is operating.
<2> Setting the subsystem clock as the source clock of the CPU/peripheral hardware clock and setting the
division ratio of the set clock (CKC register)
CSS
1
SDIV
0
1
fSUB
fSUB/2
Selection of CPU/Peripheral Hardware Clock (fCLK)
Caution When the subsystem clock is used as the CPU clock, the subsystem clock is also supplied to the
peripheral hardware (except the real-time counter, timer array unit (when fSUB/2, fSUB/4, the valid
edge of TI0mn input, or the valid edge of INTRTCI is selected as the count clock), clock
output/buzzer output, and watchdog timer). At this time, the operations of the A/D converter and
IICA are not guaranteed. For the operating characteristics of the peripheral hardware, refer to the
chapters describing the various peripheral hardware as well as CHAPTER 31 ELECTRICAL
SPECIFICATIONS.
(3) Example of setting procedure when stopping the subsystem clock
<1> Confirming the CPU clock status (CKC register)
Confirm with CLS and MCS that the CPU is operating on a clock other than the subsystem clock.
When CLS = 1, the subsystem clock is supplied to the CPU, so change the CPU clock to the internal high-
speed oscillation clock or high-speed system clock.
CLS
MCS
CPU Clock Status
0
0
Internal high-speed oscillation clock or 20 MHz internal high-speed
oscillation clock
0
1
High-speed system clock
1
×
Subsystem clock
<2> Stopping the subsystem clock (CSC register)
When XTSTOP is set to 1, subsystem clock is stopped.
Cautions 1. Be sure to confirm that CLS = 0 when setting XTSTOP to 1. In addition, stop the peripheral
hardware if it is operating on the subsystem clock.
2. The subsystem clock oscillation cannot be stopped using the STOP instruction.
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Jun 20, 2011