UPD78F1502AGK-GAK-AX Datasheet, PDF (570/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 14 SERIAL ARRAY UNIT
(1) Register setting
Figure 14-88. Example of Contents of Registers for Address Field Transmission of Simplified I²C (IIC10, IIC20)
(a) Serial output register m (SOm) … Sets only the bits of the target channel.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOm
CKOm2 CKOm1 CKOm0
SOm2 SOm1 SOm0
0 0 0 0 1 0/1 × 0/1 0 0 0 0 1 0/1 × 0/1
Start condition is generated by manipulating the SOmn bit.
(b) Serial output enable register m (SOEm) … Sets only the bits of the target channel.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOEm
SOEm2 SOEm1 SOEm0
0 0 0 0 0 0 0 0 0 0 0 0 0 0/1 × 0/1
SOEmn = 0 until the start condition is generated, and SOEmn =
1 after generation.
(c) Serial channel start register m (SSm) … Sets only the bits of the target channel is 1.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SSm
SSm3 SSm2 SSm1 SSm0
0 0 0 0 0 0 0 0 0 0 0 0 × 0/1 × 0/1
(d) Serial mode register mn (SMRmn)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMRmn CKSmn CCSmn
STSmn
SISmn0
MDmn2 MDmn1 MDmn0
0/1 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0
Operation mode of channel n
0: Transfer end interrupt
(e) Serial communication operation setting register mn (SCRmn)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SCRmn TXEmn RXEmn DAPmn CKPmn
EOCmn PTCmn1 PTCmn0 DIRmn
SLCmn1 SLCmn0
DLSmn2 DLSmn1 DLSmn0
1000000000010111
Setting of parity bit
00B: No parity
Setting of stop bit
01B: Appending 1 bit (ACK)
(f) Serial data register mn (SDRmn) (lower 8 bits: SIOr)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SDRmn
Baud rate setting
0
Transmit data setting (address + R/W)
SIOr
Remark
m: Unit number (m = 0, 1), n: Channel number (n = 0, 2), r: IIC number (r = 10, 20)
: Setting is fixed in the IIC mode, : Setting disabled (set to the initial value)
×: Bit that cannot be used in this mode (set to the initial value when not used in any mode)
0/1: Set to 0 or 1 depending on the usage of the user
R01UH0004EJ0501 Rev.5.01
554
Jun 20, 2011