UPD78F1502AGK-GAK-AX Datasheet, PDF (817/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 23 POWER-ON-CLEAR CIRCUIT
Figure 23-2. Timing of Generation of Internal Reset Signal by Power-on-Clear Circuit
and Low-Voltage Detector (2/2)
(2) When LVI is ON upon power application (option byte: LVIOFF = 0)
Supply voltage
(VDD)
VLVI
VLVI = 2.07 V (TYP.)
1.8 V^{Note 1}
VPOR = 1.61 V (TYP.)
VPDR = 1.59 V (TYP.)
0V
Internal high-speed
oscillation clock (fIH)
High-speed
system clock (fMX)
(when X1 oscillation
is selected)
CPU Operation
stops
Set LVI
(VLVI = 2.07 V)
to be used for
reset (default)
Set LVI to be
used for interrupt
Set LVI
(VLVI = 2.07 V)
to be used for
reset (default)
Change LVI
detection
voltage (VLVI)
Wait for oscillation
accuracy stabilization^{Note 3}
Wait for oscillation
accuracy stabilization^{Note 3}
Wait for oscillation
accuracy stabilization^{Note 3}
Starting oscillation is
specified by software
Starting oscillation is
specified by software
Starting oscillation is
specified by software
Normal operation
(internal high-speed
oscillation clock)^{Note 2}
Note 4 ^{Reset processing time}
POC processing time
Reset
period
(oscillation
stop)
Normal operation
(internal high-speed
oscillation clock)^{Note 2}
Reset processing time
(about 195 to 322 μs)
Reset
period
(oscillation
stop)
Normal operation
(internal high-speed
oscillation clock)^{Note 2}
Note 4 Reset processing time
POC processing time
Operation stops
Internal reset signal
Notes 1.
2.
3.
4.
The operation guaranteed range is 1.8 V ≤ VDD ≤ 5.5 V. To make the state at lower than 1.8 V reset state
when the supply voltage falls, use the reset function of the low-voltage detector, or input the low level to the
RESET pin.
The internal high-speed oscillation clock and a high-speed system clock or subsystem clock can be
selected as the CPU clock. To use the X1 clock, use the OSTC register to confirm the lapse of the
oscillation stabilization time. To use the XT1 clock, use the timer function for confirmation of the lapse of
the stabilization time.
The internal reset processing time includes the oscillation accuracy stabilization time of the internal high-
speed oscillation clock.
The following times are required between reaching the POC detection voltage (1.59 V (TYP.)) and starting
normal operation.
• When the time to reach 2.07 V (TYP.) from 1.59 V (TYP.) is less than 5.8 ms:
A POC processing time of about 2.1 to 6.2 ms is required between reaching 1.59 V (TYP.) and starting
normal operation.
• When the time to reach 2.07 V (TYP.) from 1.59 V (TYP.) is greater than 5.8 ms:
A reset processing time of about 195 to 322 μs is required between reaching 2.07 V (TYP.) and starting
normal operation.
Caution Set the low-voltage detector by software after the reset status is released (see CHAPTER 24 LOW-
VOLTAGE DETECTOR).
Remark
VLVI: LVI detection voltage
VPOR: POC power supply rise detection voltage
VPDR: POC power supply fall detection voltage
R01UH0004EJ0501 Rev.5.01
801
Jun 20, 2011