UPD78F1502AGK-GAK-AX Datasheet, PDF (619/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 15 SERIAL INTERFACE IICA
Figure 15-20. Wait (2/2)
(2) When master and slave devices both have a nine-clock wait
(master transmits, slave receives, and ACKE = 1)
Master
IICA
SCL0
Master and slave both wait
after output of ninth clock
IICA data write (cancel wait)
6
7
8
9
1
23
Slave
IICA
FFH is written to IICA or WREL is set to 1
SCL0
ACKE ^H
Transfer lines
SCL0
Wait from
master and
slave
Wait from slave
6
7
8
9
123
SDA0
D2 D1 D0 ACK
D7
D6 D5
Generate according to previously set ACKE value
Remark ACKE: Bit 2 of IICA control register 0 (IICCTL0)
WREL: Bit 5 of IICA control register 0 (IICCTL0)
A wait may be automatically generated depending on the setting of bit 3 (WTIM) of IICA control register 0 (IICCTL0).
Normally, the receiving side cancels the wait state when bit 5 (WREL) of the IICCTL0 register is set to 1 or when FFH is
written to the IICA shift register (IICA), and the transmitting side cancels the wait state when data is written to the IICA
register.
• By setting bit 1 (STT) of IICCTL0 to 1
• By setting bit 0 (SPT) of IICCTL0 to 1
R01UH0004EJ0501 Rev.5.01
603
Jun 20, 2011