UPD78F1502AGK-GAK-AX Datasheet, PDF (1010/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
Function
Details of
Function
APPENDIX C LIST OF CAUTIONS
Cautions
(38/39)
Page
Electrical DC
P10 to P15, P75, P77, P80 and P82 do not output high level in N-ch open-drain pp.885, _†
specifications characteristics
mode.
890
The maximum value of VIH of pins P10 to P15, P75, P77, P80 and P82 is VDD, even p.887 _†
in the N-ch open-drain mode.
Minimum
When VDD < 2.25 V and FSEL = 1, It is prohibited to release STOP mode during fEX p.898 _†
instruction
operation or fIH operation (This must not be performed even if the frequency is
execution time divided. The STOP mode may be released during fX operation.).
during main
system clock
operation
During
Select the normal input buffer for RxDq and the normal output mode for TxDq by p.902 _†
communication using the PIMg and POMx registers.
at same potential
(UART mode)
(dedicated baud
rate generator
output)
During
Select the normal input buffer for SIp and the normal output mode for SOp and p.903 _†
communication SCKp by using the PIMg and POMx registers.
at same potential
(CSI mode)
(master mode,
SCKp... internal
clock output)
During
Select the normal input buffer for SIp and SCKp and the normal output mode for p.904 _†
communication SOp by using the PIMg and POMx registers.
at same potential
(CSI mode)
(slave mode,
SCKp... external
clock input)
During
Select the normal input buffer and the N-ch open drain output (VDD tolerance) mode p.906 _†
communication for SDAr and the normal output mode for SCLr by using the PIMg and POMx
at same potential registers.
(simplified I²C
mode)
During
Select the TTL input buffer for RxDq and the N-ch open drain output (VDD tolerance) pp.908, _†
communication mode for TxDq by using the PIMg and POMx registers.
909, 911
at different
potential (2.5 V,
3 V) (UART
mode)
(dedicated baud
rate generator
output)
R01UH0004EJ0501 Rev.5.01
994
Jun 20, 2011