UPD78F1502AGK-GAK-AX Datasheet, PDF (113/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 3 CPU ARCHITECTURE
Address
Table 3-5. SFR List (4/5)
Special Function Register (SFR) Name
Symbol
R/W Manipulable Bit After Reset
Range
1-bit 8-bit 16-bit
FFF9DH Real-time counter control register 0
RTCC0
FFF9EH Real-time counter control register 1
RTCC1
FFF9FH Real-time counter control register 2
RTCC2
FFFA0H Clock operation mode control register
CMC
FFFA1H Clock operation status control register
CSC
FFFA2H Oscillation stabilization time counter status OSTC
register
FFFA3H Oscillation stabilization time select register OSTS
FFFA4H Clock control register
CKC
FFFA5H Clock output select register 0
CKS0
FFFA6H Clock output select register 1
CKS1
FFFA8H Reset control flag register
RESF
R/W _√
√
−
R/W _√
√
−
R/W _√
√
−
R/W _−
√
−
R/W _√
√
−
R
√
√
−
00H
00H
00H
00H
C0H
00H
√√√
√√√
√√√
√√√
√√√
√√√
R/W _−
√
−
07H
√√√
R/W _√
√
−
09H
√√√
R/W _√
√
−
00H
√√√
R/W _√
√
−
00H
√√√
R
−
√
− ^{Undefined √ √ √}
Note 1
FFFA9H Low-voltage detection register
LVIM
R/W _√
√
−
00H^{Note 2}
√√√
FFFAAH Low-voltage detection level select register LVIS
R/W _√
√
−
0EH^{Note 3}
√√√
FFFABH Watchdog timer enable register
WDTE
R/W _−
√
−
1A/9A^{Note 4} √ √ √
FFFB0H DMA SFR address register 0
DSA0
R/W _−
√
−
00H
√√√
FFFB1H DMA SFR address register 1
DSA1
R/W _−
√
−
00H
√√√
FFFB2H DMA RAM address register 0L
DRA0L DRA0 R/W _−
√
√
00H
√√√
FFFB3H DMA RAM address register 0H
DRA0H
R/W −
√
00H
√√√
FFFB4H DMA RAM address register 1L
DRA1L DRA1 R/W _−
√
√
00H
√√√
FFFB5H DMA RAM address register 1H
DRA1H
R/W −
√
00H
√√√
FFFB6H DMA byte count register 0L
DBC0L DBC0 R/W _−
√
√
00H
√√√
FFFB7H DMA byte count register 0H
DBC0H
R/W −
√
00H
√√√
FFFB8H DMA byte count register 1L
DBC1L DBC1 R/W _−
√
√
00H
√√√
FFFB9H DMA byte count register 1H
DBC1H
R/W _−
√
00H
√√√
FFFBAH DMA mode control register 0
DMC0
R/W _√
√
−
00H
√√√
FFFBBH DMA mode control register 1
DMC1
R/W _√
√
−
00H
√√√
FFFBCH DMA operation control register 0
DRC0
R/W _√
√
−
00H
√√√
FFFBDH DMA operation control register 1
DRC1
R/W _√
√
−
00H
√√√
FFFBEH Back ground event control register
BECTL
R/W _√
√
−
00H
√√√
FFFC0H
−
PFCMD^{Note 5}
−
−
−
− Undefined ^{√ √ √}
FFFC2H
−
PFS^{Note 5}
−
−
−
− Undefined ^{√ √ √}
FFFC4H
−
FLPMC^{Note 5}
−
−
−
− Undefined ^{√ √ √}
Notes 1. The reset value of RESF varies depending on the reset source.
2. The reset value of LVIM varies depending on the reset source and the setting of the option byte.
3. The reset value of LVIS varies depending on the reset source.
4. The reset value of WDTE is determined by the setting of the option byte.
5. Do not directly operate this SFR, because it is to be used in the self programming library.
R01UH0004EJ0501 Rev.5.01
97
Jun 20, 2011