UPD78F1502AGK-GAK-AX Datasheet, PDF (892/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 30 INSTRUCTION SET
Table 30-5. Operation List (17/17)
Instruction Mnemonic
Group
Operands
Condition BF
al branch
BTCLR
saddr.bit, $addr20
sfr.bit, $addr20
A.bit, $addr20
PSW.bit, $addr20
[HL].bit, $addr20
ES:[HL].bit, $addr20
saddr.bit, $addr20
sfr.bit, $addr20
A.bit, $addr20
PSW.bit, $addr20
[HL].bit, $addr20
ES:[HL].bit, $addr20
Conditional SKC
skip
SKNC
SKZ
SKNZ
SKH
SKNH
CPU
control
SEL
NOP
EI
DI
HALT
STOP
−
−
−
−
−
−
RBn
−
−
−
−
−
Bytes
4
4
3
4
3
4
4
4
3
4
3
4
2
2
2
2
2
2
2
1
3
3
2
2
Clocks
Operation
Flag
Note 1 Note 2
Z AC CY
3/5^{Note 3} − PC ← PC + 4 + jdisp8 if (saddr).bit = 0
3/5^{Note 3} − PC ← PC + 4 + jdisp8 if sfr.bit = 0
3/5^{Note 3} − PC ← PC + 3 + jdisp8 if A.bit = 0
3/5^{Note 3} − PC ← PC + 4 + jdisp8 if PSW.bit = 0
3/5^{Note 3} 6/7 PC ← PC + 3 + jdisp8 if (HL).bit = 0
4/6^{Note 3} 7/8 PC ← PC + 4 + jdisp8 if (ES, HL).bit = 0
3/5^{Note 3} − PC ← PC + 4 + jdisp8 if (saddr).bit = 1
then reset (saddr).bit
3/5^{Note 3} − PC ← PC + 4 + jdisp8 if sfr.bit = 1
then reset sfr.bit
3/5^{Note 3} − PC ← PC + 3 + jdisp8 if A.bit = 1
then reset A.bit
3/5^{Note 3} − PC ← PC + 4 + jdisp8 if PSW.bit = 1 × × ×
then reset PSW.bit
3/5^{Note 3} − PC ← PC + 3 + jdisp8 if (HL).bit = 1
then reset (HL).bit
4/6^{Note 3} − PC ← PC + 4 + jdisp8 if (ES, HL).bit = 1
then reset (ES, HL).bit
1
− Next instruction skip if CY = 1
1
− Next instruction skip if CY = 0
1
− Next instruction skip if Z = 1
1
− Next instruction skip if Z = 0
1
− Next instruction skip if (Z ∨ CY) = 0
1
− Next instruction skip if (Z ∨ CY) = 1
1
− RBS[1:0] ← n
1
− No Operation
4
− IE ← 1(Enable Interrupt)
4
− IE ← 0(Disable Interrupt)
3
− Set HALT Mode
3
− Set STOP Mode
Notes 1.
2.
3.
When the internal RAM area or SFR area is accessed, or for an instruction with no data access.
When the program memory area is accessed.
This indicates the number of clocks “when condition is not met/when condition is met”.
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the system clock control
register (CKC).
2. This number of clocks is for when the program is in the internal ROM (flash memory) area.
3. n indicates the number of register banks (n = 0 to 3)
R01UH0004EJ0501 Rev.5.01
876
Jun 20, 2011