UPD78F1502AGK-GAK-AX Datasheet, PDF (329/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 6 TIMER ARRAY UNIT
Figure 6-48. Operation Procedure When Frequency Divider Function Is Used (1/2)
TAU
default
setting
Software Operation
Sets the TAU0EN or TAU1EN bits of the PER0 register
to 1.
Channel
default
setting
Sets the TPSp register.
Determines clock frequencies of CKp0 and CKp1.
Sets the TMRpq register (determines operation mode of
channel).
Sets interval (period) value to the TDRpq register.
Clears the TOMpq bit of the TOMp register to 0 (toggle
mode).
Clears the TOLpq bit to 0.
Sets the TOpq bit and determines default level of the
TOpq output.
Sets TOEpq to 1 and enables operation of TOpq.
Clears the port register and port mode register to 0.
Operation
start
Sets the TOEpq to 1 (only when operation is resumed).
Sets the TSpq bit to 1.
The TSpq bit automatically returns to 0 because it is a
trigger bit.
During
operation
Set value of the TDRpq register can be changed.
The TCRpq register can always be read.
The TSRpq register is not used.
Set values of TOp and TOEp registers can be changed.
Set values of TMRpq, TOMp, and TOLp registers cannot
be changed.
Operation The TTpq bit is set to 1.
stop
The TTpq bit automatically returns to 0 because it is a
trigger bit.
TOEpq is cleared to 0 and value is set to the TOp
register.
Hardware Status
Power-off status
(Clock supply is stopped and writing to each register is
disabled.)
Power-on status. Each channel stops operating.
(Clock supply is started and writing to each register is
enabled.)
Channel stops operating.
(Clock is supplied and some power is consumed.)
The TOpq pin goes into Hi-Z output state.
The TOpq default setting level is output when the port mode
register is in output mode and the port register is 0.
TOpq does not change because channel stops operating.
The TOpq pin outputs the TOpq set level.
TEpq = 1, and count operation starts.
Value of TDRpq is loaded to TCRpq at the count clock
input. INTTMpq is generated and TOpq performs toggle
operation if the MDpq0 bit of the TMRpq register is 1.
Counter (TCRpq) counts down. When count value reaches
0000H, the value of TDRpq is loaded to TCRpq again, and
the count operation is continued. By detecting TCRpq =
0000H, INTTMpq is generated and TOpq performs toggle
operation.
After that, the above operation is repeated.
TEpq = 0, and count operation stops.
TCRpq holds count value and stops.
The TOpq output is not initialized but holds current status.
The TOpq pin outputs the TOpq set level.
Remark pq: Unit number + Channel number (only for channels provided with timer I/O pins)
pq = 00, 02 to 04
R01UH0004EJ0501 Rev.5.01
313
Jun 20, 2011