UPD78F1502AGK-GAK-AX Datasheet, PDF (399/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 9 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER
Figure 9-2. Format of Clock Output Select Register n (CKSn)
Address: FFFA5H (CKS0), FFFA6H (CKS1) After reset: 00H R/W
Symbol
<7>
6
5
4
3
CKSn
PCLOEn
0
0
0
CSELn
2
CCSn2
1
CCSn1
0
CCSn0
PCLOEn
0
1
PCLBUZn output enable/disable specification
Output disable (default)
Output enable
CSELn
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
CCSn2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
CCSn1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
CCSn0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
PCLBUZn output clock selection
fMAIN =
5 MHz
fMAIN =
10 MHz
fMAIN =
20 MHz
fMAIN
5 MHz
10 MHz^Note
Setting
prohibited^Note
fMAIN/2 2.5 MHz
fMAIN/2² 1.25 MHz
5 MHz
2.5 MHz
10 MHz^Note
5 MHz
fMAIN/2³ 625 kHz
1.25 MHz 2.5 MHz
fMAIN/2⁴ 312.5 kHz
625 kHz
1.25 MHz
fMAIN/2¹¹ 2.44 kHz
4.88 kHz
9.76 kHz
fMAIN/2¹² 1.22 kHz
2.44 kHz
4.88 kHz
fMAIN/2¹³ 610 Hz
1.22 kHz
2.44 kHz
fSUB
32.768 kHz
fSUB/2
fSUB/2²
fSUB/2³
16.384 kHz
8.192 kHz
4.096 kHz
fSUB/2⁴
2.048 kHz
fSUB/2⁵
1.024 kHz
fSUB/2⁶
512 Hz
fSUB/2⁷
256 Hz
Note Setting an output clock exceeding 10 MHz is prohibited when 2.7 V ≤ VDD. Setting a clock exceeding 5 MHz at
VDD < 2.7 V is also prohibited.
Cautions 1. Change the output clock after disabling clock output (PCLOEn = 0).
2. If the selected clock (fMAIN or fSUB) stops during clock output (PCLOEn = 1), the output becomes
undefined.
3. To shift to STOP mode when the main system clock is selected (CSELn = 0), set PCLOEn = 0
before executing the STOP instruction. When the subsystem clock is selected (CSELn = 1),
PCLOEn = 1 can be set because the clock can be output in STOP mode.
Remarks 1. n = 0, 1
2. fMAIN: Main system clock frequency
3. fSUB: Subsystem clock frequency
R01UH0004EJ0501 Rev.5.01
383
Jun 20, 2011