UPD78F1502AGK-GAK-AX Datasheet, PDF (92/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 3 CPU ARCHITECTURE
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Figure 3-3. Memory Map (μPD78F1502A, 78F1505A, 78F1508A, 78F1512A, 78F1515A, 78F1518A)
Data memory
space
FFFFFH
FFF00H
FFEFFH
FFEE0H
FFEDFH
FE300H
FE2FFH
FDF00H
FDEFFH
F1000H
F0FFFH
F0800H
F07FFH
F0000H
EFFFFH
Special function register (SFR)
256 bytes
General-purpose register
32 bytes
RAM^{Note 1}
7 KB
Reserved
Mirror
51.75 KB
Reserved
Extended special
function register (2nd SFR)
2 KB
Reserved
20000H
1FFFFH
Program
memory
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00000H
Flash memory
128 KB
1FFFFH
Program area
010CEH
010CDH
010C4H
010C3H
010C0H
010BFH
01080H
0107FH
On-chip debug security
ID setting area^{Note 2}
10 bytes
Option byte area^{Note 2}
4 bytes
CALLT table area
64 bytes
Vector table area
128 bytes
01000H
00FFFH
000CEH
000CDH
000C4H
000C3H
000C0H
000BFH
00080H
0007FH
Program area
On-chip debug security
ID setting area^{Note 2}
10 bytes
Option byte area^{Note 2}
4 bytes
CALLT table area
64 bytes
Vector table area
128 bytes
00000H
01FFFH
Boot cluster 1
Boot cluster 0^{Note 3}
Notes 1. Instructions can be executed from the RAM area excluding the general-purpose register area.
2. When boot swap is not used: Set the option bytes to 000C0H to 000C3H, and the on-chip debug security
IDs to 000C4H to 000CDH.
When boot swap is used: Set the option bytes to 000C0H to 000C3H and 010C0H to 010C3H, and the
on-chip debug security IDs to 000C4H to 000CDH and 010C4H to 010CDH.
3. Writing boot cluster 0 can be prohibited depending on the setting of security (see 27.7 Security Setting).
R01UH0004EJ0501 Rev.5.01
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Jun 20, 2011