UPD78F1502AGK-GAK-AX Datasheet, PDF (996/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
Function
Details of
Function
APPENDIX C LIST OF CAUTIONS
Cautions
(24/39)
Page
Serial
interface
IICA
IICA: IICA shift ^{Do not write data to IICA during data transfer.}
p.581 _†
register
Write or read IICA only during the wait period. Accessing IICA in a communication _{p.581 †}
state other than during the wait period is prohibited. When the device serves as the
master, however, IICA can be written only once after the communication trigger bit
(STT) is set to 1.
When communication is reserved, write data to IICA after the interrupt triggered by a _{p.581 †}
stop condition is detected.
PER0:
When setting serial interface IICA, be sure to set IICAEN to 1 first. If IICAEN = 0,
p.584 _†
Peripheral
writing to a control register of serial interface IICA is ignored, and, even if the register
enable register 0 ^{is read, only the default value is read.}
IICCTL0: IICA ^{If the operation of I2C is enabled (IICE = 1) when the SCL0 line is at high level, the} p.585 _†
control register 0 ^{SDA0 line is at low level, and DFC of the IICCTL1 register is 1, a start condition will}
be inadvertently detected immediately. Immediately after enabling I²C to operate
(IICE = 1), set LREL (1) by using a 1-bit memory manipulation instruction.
When bit 3 (TRC) of the IICA status register (IICS) is set to 1, WREL is set to 1 _{p.588 †}
during the ninth clock and wait is canceled, after which TRC is cleared and the SDA0
line is set to high impedance. Release the wait performed while the TRC bit is 1
(transmission status) by writing to the IICA shift register.
IICS: IICA status ^{Reading the IICS register while the address match wakeup function is enabled (WUP} p.589 _†
register
= 1) in STOP mode is prohibited. When the WUP bit is changed from 1 to 0 (wakeup
operation is stopped), regardless of the INTIICA interrupt request, the change in
status is not reflected until the next start condition or stop condition is detected. To
use the wakeup function, therefore, enable (SPIE = 1) the interrupt generated by
detecting a stop condition and read the IICS register after the interrupt has been
detected.
IICF: IICA flag ^{Write to STCEN only when the operation is stopped (IICE = 0).}
p.592 _†
register
As the bus release status (IICBSY = 0) is recognized regardless of the actual bus _{p.592 †}
status when STCEN = 1, when generating the first start condition (STT = 1), it is
necessary to verify that no third party communications are in progress in order to
prevent such communications from being destroyed.
Write to IICRSV only when the operation is stopped (IICE = 0).
p.592 _†
Setting IICWL
and IICWH on
slave side
Note the minimum fCLK operation frequency when setting the transfer clock. The _{p.597 †}
minimum fCLK operation frequency for serial interface IICA is determined according to
the mode.
Fast mode:
fCLK = 3.5 MHz (MIN.)
Standard mode: fCLK = 1 MHz (MIN.)
Canceling wait ^{If a processing to cancel a wait state executed when WUP (bit 7 of IICA control} p.604 _†
register 1 (IICCTL1)) = 1, the wait state will not be canceled.
When STCEN ^{Immediately after I2C operation is enabled (IICE = 1), the bus communication status} p.616 _†
(bit 1 of IICA flag ^{(IICBSY = 1) is recognized regardless of the actual bus status. When changing from}
register (IICF)) = ^{a mode in which no stop condition has been detected to a master device}
0
communication mode, first generate a stop condition to release the bus, then perform
master device communication.
When using multiple masters, it is not possible to perform master device
communication when the bus has not been released (when a stop condition has not
been detected).
Use the following sequence for generating a stop condition.
<1> Set IICA control register 1 (IICCTL1).
<2> Set bit 7 (IICE) of IICA control register 0 (IICCTL0) to 1.
<3> Set bit 0 (SPT) of IICCTL0 to 1.
When STCEN = ^{Immediately after I2C operation is enabled (IICE = 1), the bus released status} p.616 _†
1
(IICBSY = 0) is recognized regardless of the actual bus status. To generate the first
start condition (STT = 1), it is necessary to confirm that the bus has been released,
so as to not disturb other communications.
R01UH0004EJ0501 Rev.5.01
980
Jun 20, 2011