UPD78F1502AGK-GAK-AX Datasheet, PDF (251/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 5 CLOCK GENERATOR
(b) To stop X1 oscillation (disabling external clock input) by setting MSTOP to 1
<1> Confirming the CPU clock status (CKC register)
Confirm with CLS and MCS that the CPU is operating on a clock other than the high-speed system clock.
When CLS = 0 and MCS = 1, the high-speed system clock is supplied to the CPU, so change the CPU
clock to the subsystem clock or internal high-speed oscillation clock.
CLS
MCS
CPU Clock Status
0
0
Internal high-speed oscillation clock or 20 MHz internal high-speed
oscillation clock
0
1
High-speed system clock
1
×
Subsystem clock
<2> Setting of X1 clock oscillation stabilization time after restart of X1 clock oscillation^Note
Prior to setting "1" to MSTOP, set the OSTS register to a value greater than the count value to be
confirmed with the OSTS register after X1 clock oscillation is restarted.
<3> Stopping the high-speed system clock (CSC register)
When MSTOP is set to 1, X1 oscillation is stopped (the input of the external clock is disabled).
Note This setting is required to resume the X1 clock oscillation when the high-speed system clock is in the X1
oscillation mode.
This setting is not required in the external clock input mode.
Caution Be sure to confirm that MCS = 0 or CLS = 1 when setting MSTOP to 1. In addition, stop
peripheral hardware that is operating on the high-speed system clock.
5.6.2 Example of controlling internal high-speed oscillation clock
The following describes examples of clock setting procedures for the following cases.
(1) When restarting oscillation of the internal high-speed oscillation clock
(2) When using internal high-speed oscillation clock as CPU/peripheral hardware clock
(3) When stopping the internal high-speed oscillation clock
(1) Example of setting procedure when restarting oscillation of the internal high-speed oscillation clock^Note
<1> Setting restart of oscillation of the internal high-speed oscillation clock (CSC register)
When HIOSTOP is cleared to 0, the internal high-speed oscillation clock restarts oscillation.
Note After a reset release, the internal high-speed oscillator automatically starts oscillating and the internal high-
speed oscillation clock is selected as the CPU/peripheral hardware clock.
(2) Example of setting procedure when using internal high-speed oscillation clock as CPU/peripheral
hardware clock
<1> Restarting oscillation of the internal high-speed oscillation clock^Note
(See 5.6.2 (1) Example of setting procedure when restarting internal high-speed oscillation clock).
Note The setting of <1> is not necessary when the internal high-speed oscillation clock is operating.
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Jun 20, 2011