UPD78F1502AGK-GAK-AX Datasheet, PDF (258/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 5 CLOCK GENERATOR
Table 5-4. CPU Clock Transition and SFR Register Setting Examples (2/6)
(4) CPU operating with 20 MHz internal high-speed oscillation clock (J) after reset release (A)
(The CPU operates with the internal high-speed oscillation clock immediately after a reset release (B).)
(Setting sequence of SFR registers)
Setting Flag of SFR Register
Status Transition
(A) → (B) → (J)
DSCCTL Register ^Note
DSCON
1
Waiting for Oscillation
Stabilization
Necessary
(100 μs)
DSCCTL Register
SELDSC
1
Note Check that VDD ≥ 2.7 V and set DSCON = 1.
(5) CPU clock changing from internal high-speed oscillation clock (B) to high-speed system clock (C)
(Setting sequence of SFR registers)
Setting Flag of SFR Register
Status Transition
(B) → (C)
(X1 clock: 2 MHz ≤ fX ≤ 10 MHz)
(B) → (C)
(X1 clock: 10 MHz < fX ≤ 20 MHz)
(B) → (C)
(external main clock)
CMC Register^{Note 1}
EXCLK OSCSEL AMPH
0
1
0
0
1
1
1
1
×
OSTS
Register
CSC
Register
OSMC
Register
MSTOP
Note 2
0
FSEL
0
Note 2
0
1 ^{Note 3}
Note 2
0
0/1
OSTC
Register
Must be
checked
Must be
checked
Must
not be
checked
CKC
Regi
ster
MCM0
1
1
1
Unnecessary if these registers
are already set
Unnecessary if the CPU is operating with
the high-speed system clock
Notes 1. The CMC register can be changed only once after reset release. This setting is not necessary if it has
already been set.
2. Set the oscillation stabilization time as follows.
• Desired OSTC oscillation stabilization time ≤ Oscillation stabilization time set by OSTS
3. FSEL = 1 when fCLK > 10 MHz
If a divided clock is selected and fCLK ≤ 10 MHz, use with FSEL = 0 is possible even if fX > 10 MHz.
Caution Set the clock after the supply voltage has reached the operable voltage of the clock to be set (see
CHAPTER 31 ELECTRICAL SPECIFICATIONS).
Remarks 1. ×: don’t care
2. (A) to (K) in Table 5-4 correspond to (A) to (K) in Figure 5-15.
R01UH0004EJ0501 Rev.5.01
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Jun 20, 2011