UPD78F1502AGK-GAK-AX Datasheet, PDF (604/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 15 SERIAL INTERFACE IICA
Figure 15-6. Format of IICA Control Register 0 (IICCTL0) (4/4)
SPT
Stop condition trigger
0
Stop condition is not generated.
1
Stop condition is generated (termination of master device’s transfer).
Cautions concerning set timing
• For master reception: Cannot be set to 1 during transfer.
Can be set to 1 only in the waiting period when ACKE has been cleared to 0 and slave
has been notified of final reception.
• For master transmission: A stop condition cannot be generated normally during the acknowledge period.
Therefore, set it during the wait period that follows output of the ninth clock.
• Cannot be set to 1 at the same time as STT.
• SPT can be set to 1 only when in master mode.
• When WTIM has been cleared to 0, if SPT is set to 1 during the wait period that follows output of eight clocks, note
that a stop condition will be generated during the high-level period of the ninth clock. WTIM should be changed from
0 to 1 during the wait period following the output of eight clocks, and SPT should be set to 1 during the wait period
that follows the output of the ninth clock.
• Setting SPT to 1 and then setting it again before it is cleared to 0 is prohibited.
Condition for clearing (SPT = 0)
• Cleared by loss in arbitration
• Automatically cleared after stop condition is detected
• Cleared by LREL = 1 (exit from communications)
• When IICE = 0 (operation stop)
• Reset
Condition for setting (SPT = 1)
• Set by instruction
Caution
When bit 3 (TRC) of the IICA status register (IICS) is set to 1, WREL is set to 1 during the
ninth clock and wait is canceled, after which TRC is cleared and the SDA0 line is set to high
impedance. Release the wait performed while the TRC bit is 1 (transmission status) by
writing to the IICA shift register.
Remark Bit 0 (SPT) becomes 0 when it is read after data setting.
R01UH0004EJ0501 Rev.5.01
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Jun 20, 2011