UPD78F1502AGK-GAK-AX Datasheet, PDF (813/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 22 RESET FUNCTION
22.1 Register for Confirming Reset Source
Many internal reset generation sources exist in the 78K0R/Lx3 microcontrollers. The reset control flag register (RESF)
is used to store which source has generated the reset request.
RESF can be read by an 8-bit memory manipulation instruction.
RESET input, reset by power-on-clear (POC) circuit, and reading RESF clear TRAP, WDRF, and LVIRF.
Figure 22-5. Format of Reset Control Flag Register (RESF)
Address: FFFA8H After reset: Undefined R
Symbol
7
6
5
RESF
TRAP^{Note 1} Undefined Undefined
4
WDRF^{Note 1}
3
Undefined
2
Undefined
1
Undefined
0
LVIRF^{Note 1}
TRAP
0
1
Internal reset request by execution of illegal instruction^{Note 2}
Internal reset request is not generated, or RESF is cleared.
Internal reset request is generated.
WDRF
0
1
Internal reset request by watchdog timer (WDT)
Internal reset request is not generated, or RESF is cleared.
Internal reset request is generated.
LVIRF
0
1
Internal reset request by low-voltage detector (LVI)
Internal reset request is not generated, or RESF is cleared.
Internal reset request is generated.
Notes 1.
2.
The value after reset varies depending on the reset source.
The illegal instruction is generated when instruction code FFH is executed.
Reset by the illegal instruction execution not issued by emulation with the in-circuit emulator or on-chip
debug emulator.
Cautions 1. Do not read data by a 1-bit memory manipulation instruction.
2. Do not make a judgment based on only the read value of the RESF register 8-bit data, because
bits other than TRAP, WDRF, and LVIRF become undefined.
3. When the LVI default start function (bit 0 (LVIOFF) of 000C1H = 0) is used, LVIRF flag may
become 1 from the beginning depending on the power-on waveform.
The status of RESF when a reset request is generated is shown in Table 22-3.
Flag
TRAP
WDRF
LVIRF
Table 22-3. RESF Status When Reset Request Is Generated
Reset Source RESET Input Reset by POC Reset by Execution Reset by WDT Reset by LVI
of Illegal Instruction
Cleared (0)
Cleared (0)
Set (1)
Held
Held
Held
Set (1)
Held
Held
Held
Set (1)
R01UH0004EJ0501 Rev.5.01
797
Jun 20, 2011