UPD78F1502AGK-GAK-AX Datasheet, PDF (994/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
Function
Details of
Function
APPENDIX C LIST OF CAUTIONS
Cautions
(22/39)
Page
Configuration SIRmn: Serial Be sure to clear bits 15 to 3 to “0”.
of serial array flag clear trigger
p.457 _†
unit
register mn
SSm: Serial
Be sure to clear bits 15 to 4 to “0”.
channel start
p.459 _†
register m
STm: Serial
channel stop
Be sure to clear bits 15 to 4 to “0”.
p.460 _†
register m
SOEm: Serial
output enable
Be sure to clear bits 15 to 3 of SOE0, and bits 1 and 15 to 3 of SOE1 to “0”.
p.461 _†
register m
SOm: Serial
output register
Be sure to set bits 11 and 3 of SO0, and bits 11 to 9, 3, and 1 of SO1 to “1”. And be p.462 _†
sure to clear bits 15 to 12 and 7 to 4 of SOm to “0”.
m
SOLm: Serial
output level
Be sure to clear bits 15 to 3, 1 to “0”.
p.463 _†
register m
ISC: Input
switch control
Be sure to clear bits 7 to 5 to “0”.
p.464 _†
register
NFEN0: Noise
filter enable
Be sure to clear bits 7, 5, 3, and 1 to “0”.
p.465 _†
Operation
stop mode
register 0
Stopping the
operation by
If SAUmEN = 0, writing to a control register of serial array unit m is ignored, and, p.469 _†
even if the register is read, only the default value is read (except for input switch
units
control register (ISC), noise filter enable register (NFEN0), port input mode register
(PIM1, PIM7), port output mode register (POM1, POM7, POM8), port mode registers
3-wire serial I/O Master
(CSI00, CSI01, transmission
CSI10, CSI20) Master
communication transmission (in
(PM1, PM5, PM7, PM8), and port registers (P1, P5, P7, P8)).
After setting the SAUmEN to 1, be sure to set the SPSm register after 4 or more pp.475, _†
clocks have elapsed.
479, 481
The MDmn0 bit can be rewritten even during operation.
p.480 _†
However, rewrite it before transfer of the last bit is started, so that it will be rewritten
continuous
before the transfer end interrupt of the last transmit data.
transmission mode)
Master
After setting the SAUmEN to 1, be sure to set the SPSm register after 4 or more pp.484, _†
reception
clocks have elapsed.
487
Master
After setting the SAUmEN to 1, be sure to set the SPSm register after 4 or more pp.490, _†
transmission/ clocks have elapsed.
493, 494
reception
Master
transmission/
The MDmn0 bit can be rewritten even during operation.
p.495 _†
However, rewrite it before transfer of the last bit is started, so that it has been
reception (in rewritten before the transfer end interrupt of the last transmit data.
continuous
transmission/
reception mode)
R01UH0004EJ0501 Rev.5.01
978
Jun 20, 2011