UPD78F1502AGK-GAK-AX Datasheet, PDF (818/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 23 POWER-ON-CLEAR CIRCUIT
23.4 Cautions for Power-on-Clear Circuit
In a system where the supply voltage (VDD) fluctuates for a certain period in the vicinity of the POC detection voltage
(VPOR, VPDR), the system may be repeatedly reset and released from the reset status. In this case, the time from release
of reset to the start of the operation of the microcontroller can be arbitrarily set by taking the following action.
<Action>
After releasing the reset signal, wait for the supply voltage fluctuation period of each system by means of a software
counter that uses a timer, and then initialize the ports.
Figure 23-3. Example of Software Processing After Reset Release (1/2)
• If supply voltage fluctuation is 50 ms or less in vicinity of POC detection voltage
Reset
Initialization
processing <1>
Power-on-clear
; Check the reset source, etc.^{Note 2}
Setting timer array unit
(to measure 50 ms)
; fCLK = Internal high-speed oscillation clock (4.08 MHz (MAX.)) (default)
Source: fCLK (4.08 MHz (MAX.))/2¹¹,
where comparison value = 100: ≅ 50 ms
Timer starts (TS0n = 1).
Note 1
Clearing WDT
No
50 ms has passed?
(TMIF0n = 1?)
Yes
Initialization
processing <2>
; Initial setting for port.
Setting of division ratio of system clock,
such as setting of timer or A/D converter.
Notes 1. If reset is generated again during this period, initialization processing <2> is not started.
2. A flowchart is shown on the next page.
Remark n = 0 to 7
R01UH0004EJ0501 Rev.5.01
802
Jun 20, 2011