UPD78F1502AGK-GAK-AX Datasheet, PDF (244/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 5 CLOCK GENERATOR
Figure 5-13. Clock Generator Operation When Power Supply Voltage Is Turned On
(When LVI Default Start Function Stopped Is Set (Option Byte: LVIOFF = 1))
Power supply
voltage (VDD)
1.61 V
(TYP.)
0V
1.8 V
0.5 V/ms
(MIN.)
Internal reset signal
CPU clock
Internal high-speed
oscillation clock (fIH)
High-speed
system clock (fMX)
(when X1 oscillation
selected)
20 MHz internal
high-speed
oscillation clock (fIH20)
Subsystem clock (fSUB)
(when XT1 oscillation
selected)
<1>
<3>
<2>
Reset processing
(2.12 to 5.84 ms)
Switched by
software
SELDSC = 1
<5>
<5>
1 or 8 MHz internal high- 20 MHz internal high- 1 or 8 MHz internal high- High-speed
speed oscillation clock speed oscillation clock speed oscillation clock system clock
<5>
Subsystem
clock
Note 1
<4>
X1 clock
Starting X1 oscillation oscillation stabilization time^{Note 2}
is specified by software.
<4>
DSCON = 1
is set by software.
20 MHz internal high-speed oscillation clock
oscillation stabilization time : 100 μ s
<4>
Starting XT1 oscillation
is specified by software.
<1> When the power is turned on, an internal reset signal is generated by the power-on-clear (POC) circuit.
<2> When the power supply voltage exceeds 1.61 V (TYP.), the reset is released and the internal high-speed
oscillator automatically starts oscillation.
<3> The CPU starts operation on the internal high-speed oscillation clock ^{Note 3} after a reset processing such as waiting
for the voltage of the power supply or regulator to stabilize has been performed after reset release.
<4> Set the start of oscillation of the X1 or XT1 clock via software (see (1) in 5.6.1 Example of controlling high-
speed system clock and (1) in 5.6.3 Example of controlling subsystem clock).
<5> When switching the CPU clock to the X1 or XT1 clock, wait for the clock oscillation to stabilize, and then set
switching via software (see (3) in 5.6.1 Example of controlling high-speed system clock and (2) in 5.6.3
Example of controlling subsystem clock).
Switch to the 20 MHz internal high-speed oscillation clock by setting the DSCON bit (bit 0 of the 20 MHz internal
high-speed oscillation control register (DSCCTL)), waiting for 100 μs, and then setting the SELDSC bit to 1 by
using software ^{Note 4}.
(Notes and Cautions are listed on the next page.)
R01UH0004EJ0501 Rev.5.01
228
Jun 20, 2011