UPD78F1502AGK-GAK-AX Datasheet, PDF (286/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 6 TIMER ARRAY UNIT
(6) Timer channel start register m (TSm)
TSm is a trigger register that is used to clear a timer counter (TCRmn) and start the counting operation of each
channel.
When a bit (TSmn) of this register is set to 1, the corresponding bit (TEmn) of timer channel enable status register
m (TEm) is set to 1. TSmn is a trigger bit and cleared immediately when TEmn = 1.
TSm can be set by a 16-bit memory manipulation instruction.
The lower 8 bits of TSm can be set with a 1-bit or 8-bit memory manipulation instruction with TSmL.
Reset signal generation clears this register to 0000H.
Figure 6-10. Format of Timer Channel Start Register m (TSm)
Address: F01B2H, F01B3H After reset: 0000H R/W
Symbol
15 14 13 12 11 10 9
TS0
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0 TS07 TS06 TS05 TS04 TS03 TS02 TS01 TS00
Address: F01DAH, F01DBH After reset: 0000H R/W
Symbol
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
TS1
0
0
0
0
0
0
0
0
0
0
0
0 TS13 TS12 TS11 TS10
TSmn
Operation enable (start) trigger of channel n
0 No trigger operation
1 TEmn is set to 1 and the count operation becomes enabled.
The TCRmn count operation start in the count operation enabled state varies depending on each operation
mode (see Table 6-4).
Caution Be sure to clear bits 15 to 8 of TS0 and bits 15 to 4 of TS1 to “0”.
Remarks 1. When the TSm register is read, 0 is always read.
2. mn: Unit number + Channel number
m = 0, 1, mn = 00 to 07, 10 to 13
R01UH0004EJ0501 Rev.5.01
270
Jun 20, 2011