UPD78F1502AGK-GAK-AX Datasheet, PDF (345/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 6 TIMER ARRAY UNIT
Figure 6-61. Operation Procedure When PWM Function Is Used (2/2)
Software Operation
Operation
start
Sets TOEmp (slave) to 1 (only when operation is
resumed).
The TSmn (master) and TSmp (slave) bits of the TSm
register are set to 1 at the same time.
The TSmn and TSmp bits automatically return to 0
because they are trigger bits.
During
operation
Set values of the TMRmn and TMRmp registers and
TOMmn, TOMmp, TOLmn, and TOLmp bits cannot be
changed.
Set values of the TDRmn and TDRmp registers can be
changed after INTTMmn of the master channel is
generated.
The TCRmn and TCRmp registers can always be read.
The TSRmn and TSRmp registers are not used.
Set values of the TOm and TOEm registers cannot be
changed.
Operation
stop
The TTmn (master) and TTmp (slave) bits are set to 1 at
the same time.
The TTmn and TTmp bits automatically return to 0
because they are trigger bits.
TOEmp of slave channel is cleared to 0 and value is set
to the TOmp register.
TAU stop
To hold the TOmp pin output levels
Clears TOmp bit to 0 after the value to
be held is set to the port register.
When holding the TOmp pin output levels is not
necessary
Switches the port mode register to input mode.
The TAU0EN or TAU1EN bits of the PER0 register is
cleared to 0.
Hardware Status
TEmn = 1, TEmp = 1
When the master channel starts counting, INTTMmn is
generated. Triggered by this interrupt, the slave
channel also starts counting.
The counter of the master channel loads the TDRmn
value to TCRmn, and counts down. When the count
value reaches TCRmn = 0000H, INTTMmn output is
generated. At the same time, the value of the TDRmn
register is loaded to TCRmn, and the counter starts
counting down again.
At the slave channel, the value of TDRmp is loaded to
TCRmp, triggered by INTTMmn of the master channel,
and the counter starts counting down. The output level of
TOmp becomes active one count clock after generation of
the INTTMmn output from the master channel. It
becomes inactive when TCRmp = 0000H, and the
counting operation is stopped.
After that, the above operation is repeated.
TEmn, TEmp = 0, and count operation stops.
TCRmn and TCRmp hold count value and stops.
The TOmp output is not initialized but holds current
status.
The TOmp pin outputs the TOmp set level.
The TOmp pin output levels is held by port function.
The TOmp pin output levels go are into Hi-Z output state.
Power-off status
All circuits are initialized and SFR of each channel is
also initialized.
(The TOmp bit is cleared to 0 and the TOmp pin is set
to port mode.)
Remarks 1.
2.
3.
78K0R/LF3:
• m = 0, n = 0, 2, 6, p = n+1, TO00 to TO04, and TO07 pins
78K0R/LG3:
• m = 0, n = 0, 2, 4, 6, p = n+1, TO00 to TO07 pins
78K0R/LH3:
• m = 0, n = 0, 2, 4, 6, p = n+1, TO00 to TO07 pins
• m = 1, n = 0, 2, p = n+1, TO10 to TO13 pins
R01UH0004EJ0501 Rev.5.01
329
Jun 20, 2011