UPD78F1502AGK-GAK-AX Datasheet, PDF (334/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 6 TIMER ARRAY UNIT
Figure 6-52. Operation Procedure When Input Pulse Interval Measurement Function Is Used
TAU
default
setting
Software Operation
Sets the TAU0EN or TAU1EN bits of the PER0 register
to 1.
Sets the TPSp register.
Determines clock frequencies of CKp0 and CKp1.
Channel
default
setting
Sets the TMRpq register (determines operation mode of
channel).
Operation Sets TSpq bit to 1.
start
The TSpq bit automatically returns to 0 because it is a
trigger bit.
During
operation
Set values of only the CISpq1 and CISpq0 bits of the
TMRpq register can be changed.
The TDRpq register can always be read.
The TCRpq register can always be read.
The TSRpq register can always be read.
Set values of TOMp, TOLp, TOp, and TOEp registers
cannot be changed.
Operation The TTpq bit is set to 1.
stop
The TTpq bit automatically returns to 0 because it is a
trigger bit.
TAU stop The TAU0EN or TAU1EN bits of the PER0 register is
cleared to 0.
Hardware Status
Power-off status
(Clock supply is stopped and writing to each register is
disabled.)
Power-on status. Each channel stops operating.
(Clock supply is started and writing to each register is
enabled.)
Channel stops operating.
(Clock is supplied and some power is consumed.)
TEpq = 1, and count operation starts.
TCRpq is cleared to 0000H at the count clock input.
When the MDpq0 bit of the TMRpq register is 1,
INTTMpq is generated.
Counter (TCRpq) counts up from 0000H. When the TIpq
pin input valid edge is detected, the count value is
transferred (captured) to TDRpq. At the same time,
TCRpq is cleared to 0000H, and the INTTMpq signal is
generated.
If an overflow occurs at this time, the OVFpq bit of the
TSRpq register is set; if an overflow does not occur, the
OVFpq bit is cleared.
After that, the above operation is repeated.
TEpq = 0, and count operation stops.
TCRpq holds count value and stops.
The OVFpq bit of the TSRpq register is also held.
Power-off status
All circuits are initialized and SFR of each channel is
also initialized.
Remark
pq: Unit number + Channel number (only for channels provided with timer I/O pins)
78K0R/LF3: p = 0, pq = 00 to 04, 07
78K0R/LG3: p = 0, pq = 00 to 07
78K0R/LH3: p = 0, 1, pq = 00 to 07, 10 to 13
R01UH0004EJ0501 Rev.5.01
318
Jun 20, 2011