UPD78F1502AGK-GAK-AX Datasheet, PDF (507/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 14 SERIAL ARRAY UNIT
Figure 14-41. Procedure for Resuming Master Transmission/Reception
Starting setting for resumption
(Essential)
Port manipulation
(Selective) ^{Changing setting of SPSm register}
Disable data output and clock output of
the target channel by setting a port
register and a port mode register.
Change the setting if an incorrect division
ratio of the operation clock is set.
(Selective) ^{Changing setting of SDRmn register}
Change the setting if an incorrect
transfer baud rate is set.
(Selective) ^{Changing setting of SMRmn register}
(Selective) ^{Changing setting of SCRmn register}
(Selective)
Clearing error flag
(Selective) ^{Changing setting of SOEm register}
Change the setting if the setting of the
SMRmn register is incorrect.
Change the setting if the setting of the
SCRmn register is incorrect.
Cleared by using SIRmn register if FEF,
PEF, or OVF flag remains set.
Set the SOEm register and stop the
output of the target channel.
(Selective) ^{Changing setting of SOm register}
(Selective) ^{Changing setting of SOEm register}
(Essential)
Port manipulation
(Essential)
Writing to SSm register
(Essential)
Starting communication
Manipulate the SOmn and CKOmn bits
and set an initial output level.
Set the SOEm register and enable the
output of the target channel.
Enable data output and clock output of
the target channel by setting a port
register and a port mode register.
Set the SSmn bit of the target channel to
1 and set SEmn to 1.
Set transmit data to the SIOp register (bits 7
to 0 of the SDRmn register) and start
communication.
R01UH0004EJ0501 Rev.5.01
491
Jun 20, 2011