UPD78F1502AGK-GAK-AX Datasheet, PDF (827/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 24 LOW-VOLTAGE DETECTOR
24.4.1 When used as reset
(1) When detecting level of supply voltage (VDD)
(a) When LVI default start function stopped is set (LVIOFF = 1)
• When starting operation
<1> Mask the LVI interrupt (LVIMK = 1).
<2> Clear bit 2 (LVISEL) of the low-voltage detection register (LVIM) to 0 (detects level of supply voltage
(VDD)) (default value).
<3> Set the detection voltage using bits 3 to 0 (LVIS3 to LVIS0) of the low-voltage detection level selection
register (LVIS).
<4> Set bit 7 (LVION) of LVIM to 1 (enables LVI operation).
<5> Use software to wait for the following periods of time (Total 210 μs).
• Operation stabilization time (10 μs (MAX.))
• Minimum pulse width (200 μs (MIN.))
<6> Wait until it is checked that (supply voltage (VDD) ≥ detection voltage (VLVI)) by bit 0 (LVIF) of LVIM.
<7> Set bit 1 (LVIMD) of LVIM to 1 (generates reset when the level is detected).
Figure 24-5 shows the timing of the internal reset signal generated by the low-voltage detector. The numbers in
this timing chart correspond to <1> to <7> above.
Cautions 1. Be sure to execute <1>. When LVIMK = 0, an interrupt may occur immediately after the
processing in <4>.
2. If supply voltage (VDD) ≥ detection voltage (VLVI) when LVIMD is set to 1, an internal reset
signal is not generated.
• When stopping operation
Be sure to clear (0) LVIMD and then LVION by using a 1-bit memory manipulation instruction.
R01UH0004EJ0501 Rev.5.01
811
Jun 20, 2011