UPD78F1502AGK-GAK-AX Datasheet, PDF (472/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 14 SERIAL ARRAY UNIT
Figure 14-9. Format of Serial Status Register mn (SSRmn) (2/2)
Address: F0100H, F0101H (SSR00) to F0106H, F0107H (SSR03), After reset: 0000H R
F0140H, F0141H (SSR10), F0142H, F0143H (SSR11),
F0144H, F0145H (SSR12), F0146H, F0147H (SSR13)
Symbol
15 14 13 12 11 10 9
8
7
6
5
4
SSRmn
0
0
0
0
0
0
0
0
0 TSF BFF 0
mn mn
3
2
1
0
0 FEF PEF OVF
mn mn mn
Note
Note
Note
FEF
Framing error detection flag of channel n
mn
0 No error occurs.
1 A framing error occurs during UART reception.
<Framing error cause>
A framing error occurs if the stop bit is not detected upon completion of UART reception.
This is a cumulative flag and is not cleared until 1 is written to the FECTmn bit of the SIRmn register.
PEF
Parity error detection flag of channel n
mn
0 Error does not occur.
1 A parity error occurs during UART reception or ACK is not detected during I²C transmission.
<Parity error cause>
• A parity error occurs if the parity of transmit data does not match the parity bit on completion of UART
reception.
• ACK is not detected if the ACK signal is not returned from the slave in the timing of ACK reception
during I²C transmission.
This is a cumulative flag and is not cleared until 1 is written to the PECTmn bit of the SIRmn register.
OVF
mn
Overrun error detection flag of channel n
0 No error occurs.
1 An overrun error occurs.
<Causes of overrun error>
• Receive data stored in the SDRmn register is not read and transmit data is written or the next receive
data is written.
• Transmit data is not ready for slave transmission or reception in the CSI mode.
This is a cumulative flag and is not cleared until 1 is written to the OVCTmn bit of the SIRmn register.
Note Only SSR12 register does not have FET12, PET12, and OVF12.
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3)
R01UH0004EJ0501 Rev.5.01
456
Jun 20, 2011