UPD78F1502AGK-GAK-AX Datasheet, PDF (807/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 22 RESET FUNCTION
Figure 22-4. Timing of Reset in STOP Mode by RESET Input
STOP instruction execution
Wait for oscillation
accuracy stabilization
Internal high-speed
oscillation clock
High-speed system clock
(when X1 oscillation is selected)
Starting X1 oscillation is specified by software.
CPU clock
RESET
Normal
operation
Internal reset signal
Stop status
Reset period
(oscillation stop) (oscillation stop)
Normal operation
(internal high-speed oscillation clock)
Reset processing
(about 2.1 to 5.8 ms)
Port pin
(except P130)
Port pin
(P130)
Delay
Delay
(about 30 to 170 μs)
Hi-Z
Note
Note Set P130 to high-level output by software.
Remarks 1. When reset is effected, P130 outputs a low level. If P130 is set to output a high level before reset is
effected, the output signal of P130 can be dummy-output as the CPU reset signal.
2. For the reset timing of the power-on-clear circuit and low-voltage detector, see CHAPTER 23 POWER-
ON-CLEAR CIRCUIT and CHAPTER 24 LOW-VOLTAGE DETECTOR.
R01UH0004EJ0501 Rev.5.01
791
Jun 20, 2011