UPD78F1502AGK-GAK-AX Datasheet, PDF (636/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 15 SERIAL INTERFACE IICA
Figure 15-29. Master Operation in Multi-Master System (2/3)
A Enables reserving communication.
STT = 1
Wait
Prepares for starting communication
(generates a start condition).
Secure wait time^Note by software.
MSTS = 1?
No
Yes
INTIICA
interrupt occurs?
Yes
Wait state after stop condition
No _{EXC = 1 or COI =1?}
was detected and start condition
was generated by the communication
Yes
reservation function.
C
Slave operation
No
Waits for bus release
(communication being reserved).
B _{Disables reserving communication.}
IICBSY = 0?
No
Yes
D
STT = 1
Prepares for starting communication
(generates a start condition).
Wait^Note
STCF = 0?
No
Yes
C
INTIICA
interrupt occurs?
Yes
EXC = 1 or COI =1?
Yes
Slave operation
No
Waits for bus release
No
Detects a stop condition.
D
Note The wait time is calculated as follows.
(IICWL setting value + IICWH setting value + 4 clocks) / fCLK + tF × 2
Remark
IICWL: IICA low-level width setting register
IICWH: IICA high-level width setting register
tF:
SDA0 and SCL0 signal falling times
fCLK: CPU/peripheral hardware clock frequency
R01UH0004EJ0501 Rev.5.01
620
Jun 20, 2011