UPD78F1502AGK-GAK-AX Datasheet, PDF (739/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 18 DMA CONTROLLER
(2) DMA operation control register n (DRCn)
DRCn is a register that is used to enable or disable transfer of DMA channel n.
Rewriting bit 7 (DENn) of this register is prohibited during operation (when DSTn = 1).
DRCn can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 18-5. Format of DMA Operation Control Register n (DRCn)
Address: FFFBCH (DRC0), FFFBDH (DRC1) After reset: 00H R/W
Symbol
<7>
6
5
4
3
2
1
DRCn
DENn
0
0
0
0
0
0
<0>
DSTn
DENn
DMA operation enable flag
0
Disables operation of DMA channel n (stops operating cock of DMA).
1
Enables operation of DMA channel n.
DMAC waits for a DMA trigger when DSTn = 1 after DMA operation is enabled (DENn = 1).
DSTn
DMA transfer mode flag
0
DMA transfer of DMA channel n is completed.
1
DMA transfer of DMA channel n is not completed (still under execution).
DMAC waits for a DMA trigger when DSTn = 1 after DMA operation is enabled (DENn = 1).
When a software trigger (STGn) or the start source trigger set by IFCn3 to IFCn0 is input, DMA transfer is started.
When DMA transfer is completed after that, this bit is automatically cleared to 0.
Write 0 to this bit to forcibly terminate DMA transfer under execution.
Cautions 1. The DSTn flag is automatically cleared to 0 when a DMA transfer is completed.
Writing the DENn flag is enabled only when DSTn = 0. When a DMA transfer is terminated
without waiting for generation of the interrupt (INTDMAn) of DMAn, therefore, set DSTn to 0
and then DENn to 0 (for details, refer to 18.5.7 Forced termination by software).
2. When the FSEL bit of the OSMC register has been set to 1, do not enable (DENn = 1) DMA
operation for at least three clocks after the setting.
Remark n: DMA channel number (n = 0, 1)
R01UH0004EJ0501 Rev.5.01
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Jun 20, 2011