UPD78F1502AGK-GAK-AX Datasheet, PDF (806/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 22 RESET FUNCTION
Figure 22-2. Timing of Reset by RESET Input
Internal high-speed
oscillation clock
High-speed system clock
(when X1 oscillation is selected)
CPU clock
Normal operation
RESET
Wait for oscillation
accuracy stabilization
Reset period
(oscillation stop)
Starting X1 oscillation is specified by software.
Normal operation
(internal high-speed oscillation clock)
Reset processing
(about 2.1 to 5.8 ms)
Internal reset signal
Port pin
(except P130)
Delay
Delay
(about 30 to 170 μs)
Hi-Z
Port pin
(P130)
Note
Note Set P130 to high-level output by software.
Remark When reset is effected, P130 outputs a low level. If P130 is set to output a high level before reset is
effected, the output signal of P130 can be dummy-output as the CPU reset signal.
Figure 22-3. Timing of Reset Due to Watchdog Timer Overflow
Wait for oscillation
accuracy stabilization
Internal high-speed
oscillation clock
High-speed system clock
(when X1 oscillation is selected)
CPU clock
Watchdog timer
overflow
Normal operation
Reset period
(oscillation stop)
Starting X1 oscillation is specified by software.
Normal operation
(internal high-speed oscillation clock)
Reset processing
(about 195 to 322 μs)
Internal reset signal
Port pin
(except P130)
Port pin
(P130)
Hi-Z
Note
Note Set P130 to high-level output by software.
Caution A watchdog timer internal reset resets the watchdog timer.
Remark When reset is effected, P130 outputs a low level. If P130 is set to output a high level before reset is
effected, the output signal of P130 can be dummy-output as the CPU reset signal.
R01UH0004EJ0501 Rev.5.01
790
Jun 20, 2011