UPD78F1502AGK-GAK-AX Datasheet, PDF (618/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 15 SERIAL INTERFACE IICA
15.5.6 Wait
The wait is used to notify the communication partner that a device (master or slave) is preparing to transmit or receive
data (i.e., is in a wait state).
Setting the SCL0 pin to low level notifies the communication partner of the wait state. When wait state has been
canceled for both the master and slave devices, the next data transfer can begin.
Figure 15-20. Wait (1/2)
(1) When master device has a nine-clock wait and slave device has an eight-clock wait
(master transmits, slave receives, and ACKE = 1)
Master
IICA
Master returns to high
impedance but slave
is in wait state (low level).
Wait after output
of ninth clock
IICA data write (cancel wait)
SCL0
6789
123
Slave
IICA
SCL0
Wait after output
of eighth clock
FFH is written to IICA or WREL is set to 1
ACKE ^H
Transfer lines
SCL0
Wait from slave Wait from master
678
9
123
SDA0
D2 D1 D0
ACK
D7 D6 D5
R01UH0004EJ0501 Rev.5.01
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Jun 20, 2011