UPD78F1502AGK-GAK-AX Datasheet, PDF (628/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 15 SERIAL INTERFACE IICA
15.5.14 Communication reservation
(1) When communication reservation function is enabled (bit 0 (IICRSV) of IICA flag register (IICF) = 0)
To start master device communications when not currently using a bus, a communication reservation can be made
to enable transmission of a start condition when the bus is released. There are two modes under which the bus is
not used.
• When arbitration results in neither master nor slave operation
• When an extension code is received and slave operation is disabled (ACK is not returned and the bus was
released by setting bit 6 (LREL) of IICA control register 0 (IICCTL0) to 1 and saving communication).
If bit 1 (STT) of IICCTL0 is set to 1 while the bus is not used (after a stop condition is detected), a start condition is
automatically generated and wait state is set.
If an address is written to the IICA shift register (IICA) after bit 4 (SPIE) of IICCTL0 was set to 1, and it was
detected by generation of an interrupt request signal (INTIICA) that the bus was released (detection of the stop
condition), then the device automatically starts communication as the master. Data written to IICA before the stop
condition is detected is invalid.
When STT has been set to 1, the operation mode (as start condition or as communication reservation) is
determined according to the bus status.
• If the bus has been released ........................................ a start condition is generated
• If the bus has not been released (standby mode)......... communication reservation
Check whether the communication reservation operates or not by using MSTS (bit 7 of the IICA status register
(IICS)) after STT is set to 1 and the wait time elapses.
Use software to secure the wait time calculated by the following expression.
Wait time from setting STT = 1 to checking the MSTS flag:
(IICWL setting value + IICWH setting value + 4 clocks) / fCLK + tF × 2
Remark
IICWL: IICA low-level width setting register
IICWH: IICA high-level width setting register
tF:
SDA0 and SCL0 signal falling times
fCLK: CPU/peripheral hardware clock frequency
R01UH0004EJ0501 Rev.5.01
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Jun 20, 2011