UPD78F1502AGK-GAK-AX Datasheet, PDF (790/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 21 STANDBY FUNCTION
(1) Oscillation stabilization time counter status register (OSTC)
This is the register that indicates the count status of the X1 clock oscillation stabilization time counter.
The X1 clock oscillation stabilization time can be checked in the following case,
• If the X1 clock starts oscillation while the internal high-speed oscillation clock or subsystem clock is being used
as the CPU clock.
• If the STOP mode is entered and then released while the internal high-speed oscillation clock is being used as
the CPU clock with the X1 clock oscillating.
OSTC can be read by a 1-bit or 8-bit memory manipulation instruction.
When reset is released (reset by RESET input, POC, LVI, WDT, and executing an illegal instruction), the STOP
instruction and MSTOP (bit 7 of CSC register) = 1 clear this register to 00H.
Figure 21-1. Format of Oscillation Stabilization Time Counter Status Register (OSTC)
Address: FFFA2H After reset: 00H R
Symbol
7
6
5
4
3
2
1
0
OSTC
MOST MOST MOST MOST MOST MOST MOST MOST
8
9
10
11
13
15
17
18
MOST MOST MOST MOST MOST MOST MOST MOST
8
9
10
11
13
15
17
18
Oscillation stabilization time status
fX = 10 MHz fX = 20 MHz
0
0
0
0
0
0
0
0 2⁸/fX max. 25.6 μs max. 12.8 μs max.
1
0
0
0
0
0
0
0 2⁸/fX min. 25.6 μs min. 12.8 μs min.
1
1
0
0
0
0
0
0 2⁹/fX min. 51.2 μs min. 25.6 μs min.
1
1
1
0
0
0
0
0 2¹⁰/fX min. 102.4 μs min. 51.2 μs min.
1
1
1
1
0
0
0
0 2¹¹/fX min. 204.8 μs min. 102.4 μs min.
1
1
1
1
1
0
0
0 2¹³/fX min. 819.2 μs min. 409.6 μs min.
1
1
1
1
1
1
0
0 2¹⁵/fX min. 3.27 ms min. 1.64 ms min.
1
1
1
1
1
1
1
0 2¹⁷/fX min. 13.11 ms min. 6.55 ms min.
1
1
1
1
1
1
1
1 2¹⁸/fX min. 26.21 ms min. 13.11 ms min.
Cautions 1. After the above time has elapsed, the bits are set to 1 in order from MOST8 and
remain 1.
2. The oscillation stabilization time counter counts up to the oscillation stabilization
time set by OSTS. If the STOP mode is entered and then released while the internal
high-speed oscillation clock is being used as the CPU clock, set the oscillation
stabilization time as follows.
• Desired OSTC oscillation stabilization time ≤ Oscillation stabilization time set
by OSTS
Note, therefore, that only the status up to the oscillation stabilization time set by
OSTS is set to OSTC after STOP mode is released.
3. The X1 clock oscillation stabilization wait time does not include the time until clock
oscillation starts (“a” below).
STOP mode release
X1 pin voltage
waveform
a
Remark fX: X1 clock oscillation frequency
R01UH0004EJ0501 Rev.5.01
774
Jun 20, 2011