UPD78F1502AGK-GAK-AX Datasheet, PDF (284/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 6 TIMER ARRAY UNIT
(4) Timer status register pq (TSRpq)
TSRpq indicates the overflow status of the counter of channel n.
TSRpq is valid only in the capture mode (MDpq3 to MDpq1 = 010B) and capture & one-count mode (MDpq3 to
MDpq1 = 110B). It will not be set in any other mode. See Table 6-3 for the operation of the OVFpq bit in each
operation mode and set/clear conditions.
TSRpq can be read by a 16-bit memory manipulation instruction.
The lower 8 bits of TSRpq can be set with an 8-bit memory manipulation instruction with TSRpqL.
Reset signal generation clears this register to 0000H.
Figure 6-8. Format of Timer Status Register pq (TSRpq)
Address: F01A0H, F01A1H (TSR00) to F01AEH, F01AFH (TSR07) After reset: 0000H R
F01D0H, F01D1H (TSR10) to F01D6H, F01D7H (TSR13)
Symbol
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
TSRpq
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0 OVF
pq
OVF
pq
Counter overflow status of channel q
0 Overflow does not occur.
1 Overflow occurs.
When OVFpq = 1, this flag is cleared (OVFpq = 0) when the next value is captured without overflow.
Remark
pq: Unit number + Channel number (only for channels provided with timer I/O pins)
78K0R/LF3: pq = 00 to 04, 07
78K0R/LG3: pq = 00 to 07
78K0R/LH3: pq = 00 to 07, 10 to 13
Table 6-3. OVFpq Bit Operation and Set/Clear Conditions in Each Operation Mode
Timer operation mode
• Capture mode
• Capture & one-count mode
• Interval timer mode
• Event counter mode
• One-count mode
OVFpq
Set/clear conditions
clear When no overflow has occurred upon capturing
set
When an overflow has occurred upon capturing
clear
−
(Use prohibited, not set/cleared)
set
Remark The OVFpq bit does not change immediately after the counter has overflowed, but changes upon the
subsequent capture.
R01UH0004EJ0501 Rev.5.01
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Jun 20, 2011