UPD78F1502AGK-GAK-AX Datasheet, PDF (440/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 11 D/A CONVERTER (μ PD78F150xA only)
<6> Set the DACEn bit of the DAM register to 1 (D/A conversion enable).
After the wait time (20 μs or more) elapses, D/A conversion starts, and then, after the settling time (18 μs (max.))
elapses, the D/A converted analog voltage value is output from the ANOn pin.
<7> Set the DAMDn bit of the DAM register to 1 (real-time output mode).
Steps <1> to <7> above constitute the initial settings.
<8> Operate timer channel m.
<9> Generation of the INTTM0m signals starts D/A conversion and the D/A converted analog voltage value will be
output from the ANOn pin after a settling time (18 μs (max.)) has elapsed.
<10> Afterward, the value set to the DACSWn or DACSn register will be output at the generation timing of the
INTTM0m signals.
Set the analog voltage value to be output to the ANOn pin, to the DACSWn or DACSn register before performing
the next D/A conversion (INTTM0m signal are generated).
When the DACEn bit of the DAM register is set to 0 (D/A conversion operation stop), D/A conversion stops, the
ANOn pin goes into a high-impedance state when the PM11n bit of the PM11 register = 1 (input mode), and the
ANOn pin outputs the set value of the P11 register when the PM11n bit = 0 (output mode).
Cautions 1. Even if 1, 0, and then 1 is set to the DACEn bit, there is a wait after 1 is set for the last time.
2. Make the interval between each generation of the INTTM0m signal longer than the settling time. If
an INTTM0m signal is generated during the settling time, D/A conversion is aborted and
reconversion starts.
3. Even if the generation of the INTTM0m signal and rewriting the DACSWn or DACSn register
conflict, the D/A conversion result is output.
Remark n = 0, 1
11.5 Cautions for D/A Converter
Observe the following cautions when using the D/A converter.
(1) The digital port I/O function, which is the alternate function of the ANO0 and ANO1 pins, does not operate during D/A
conversion.
When the P11 register is read during D/A conversion, 0 is read in input mode and the set value of the P11 register is
read in output mode. If the digital output mode is set, no output data is output to pins.
(2) The operation of the D/A converter continues in the HALT and STOP mode. To lower the power consumption,
therefore, clear the DACEn bit of the DAM register to 0 (D/A conversion stop), and execute HALT or STOP instruction.
(3) Rewriting DACSWn (n = 0, 1) during A/D conversion is prohibited when both the positive reference voltage of the A/D
converter (ADREFP) and the positive reference voltage of the D/A converter (DAREFP) are the voltage reference output
(VREFOUT) (VRSEL = 1 and DAREF = 1). Rewrite it when conversion operation is stopped (ADCS = 0).
Remark n = 0, 1, m = 4, 5
R01UH0004EJ0501 Rev.5.01
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Jun 20, 2011