UPD78F1502AGK-GAK-AX Datasheet, PDF (359/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 6 TIMER ARRAY UNIT
Figure 6-71. Operation Procedure When Multiple PWM Output Function Is Used (2/2)
Software Operation
Hardware Status
Operation Sets TOEmp and TOEmq (slave) to 1 (only when
start
operation is resumed).
The TSmn bit (master), and TSmp and TSmq (slave) bits
of the TSm register are set to 1 at the same time.
The TSmn, TSmp, and TSmq bits automatically return
to 0 because they are trigger bits.
TEmn = 1, TEmp, TEmq = 1
When the master channel starts counting, INTTMmn is
generated. Triggered by this interrupt, the slave
channel also starts counting.
During
operation
Set values of the TMRmn, TMRmp, and TMRmq registers
and TOMmn, TOMmp, TOMmq, TOLmn, TOLmp, and
TOLmq bits cannot be changed.
Set values of the TDRmn, TDRmp, and TDRmq registers
can be changed after INTTMmn of the master channel is
generated.
The TCRmn, TCRmp, and TCRmq registers can always
be read.
The TSRmn, TSRmp, and TSRmq registers are not used.
Set values of the TOm and TOEm registers can be
changed.
The counter of the master channel loads the TDRmn value
to TCRmn and counts down. When the count value
reaches TCRmn = 0000H, INTTMmn output is generated.
At the same time, the value of the TDRmn register is loaded
to TCRmn, and the counter starts counting down again.
At the slave channel 1, the values of TDRmp are
transferred to TCRmp, triggered by INTTMmn of the master
channel, and the counter starts counting down. The output
levels of TOmp become active one count clock after
generation of the INTTMmn output from the master
channel. It becomes inactive when TCRmp = 0000H, and
the counting operation is stopped.
At the slave channel 2, the values of TDRmq are
transferred to TDRmq, triggered by INTTMmn of the master
channel, and the counter starts counting down. The output
levels of TOmq become active one count clock after
generation of the INTTMmn output from the master
channel. It becomes inactive when TCRmq = 0000H, and
the counting operation is stopped.
After that, the above operation is repeated.
Operation
stop
The TTmn bit (master), TTmp, and TTmq (slave) bits are
set to 1 at the same time.
The TTmn, TTmp, and TTmq bits automatically return
to 0 because they are trigger bits.
TEmn, TEmp, and TEmq = 0, and count operation stops.
TCRmn, TCRmp and TCRmq hold count value and stops.
The TOmp and TOmq outputs are not initialized but
holds current status.
TOEmp or TOEmq of slave channel is cleared to 0
and value is set to the TOmp and TOmq registers.
TAU stop
To hold the TOmp and TOmq pins output levels
Clears TOmp and TOmq bits to 0 after
the value to be held is set to the port register.
When holding the TOmp and TOmq pins output levels is
not necessary
Switches the port mode register to input mode.
The TOmp and TOmq pins output the TOmp and TOmq
set levels.
The TOmp and TOmq pins output levels are held by port
function.
The TOmp and TOmq pins output levels go into Hi-Z output
state.
The TAU0EN or TAU1EN bits of the PER0 register is
cleared to 0.
Power-off status
All circuits are initialized and SFR of each channel is
also initialized.
(The TOmp and TOmq bits are cleared to 0 and the
TOmp and TOmq pins are set to port mode.)
R01UH0004EJ0501 Rev.5.01
343
Jun 20, 2011