UPD78F1502AGK-GAK-AX Datasheet, PDF (588/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 14 SERIAL ARRAY UNIT
Table 14-6. Relationship between register settings and pins (Channel 1 of unit 0: CSI01, UART0 reception)
SE MD MD SOE SO01 CKO TXE RXE PM P75 PM P76 PM P77 PM P81 Operation
01 012 011 01
Note1
01 01 01 75
76
77
Note2
81
Note2
mode
SCK01/
KR5/
P75
Pin Function
SI01/
KR6/
P76
SO01/ RxD0/SI00/
KR7/
P77
INTP9/
P81^Note2
0 00
01
1 00
01
0 1 10
0 1 10
1 0/1 1 1
Note4
1 0/1 1 1
Note4
0 1 0/1 0
Note4
1 0/1 0/1 1
Note4 Note4
1 0/1 0/1 1
Note4 Note4
0 1 10
0 × × × × × × × × Operation KR5/ KR6/P76 KR7/ SI00/
Note3 Note3 Note3 Note3 Note3 Note3 Note3 Note3
stop
P75
P77 INTP9/P80
mode
1 1 × 1 × × × × × Slave SCK01 SI01 KR7/ SI00/
Note3 Note3 Note3 Note3 _{CSI01 (input)}
P77 INTP9/P80
reception
0 1 × × × 0 1 × × Slave SCK01 KR6/P76 SO01 SI00/
Note3 Note3
Note3 Note3 _{CSI01 (input)}
INTP9/P80
transmission
1 1 × 1 × 0 1 × × Slave SCK01 SI01 SO01 SI00/
Note3 Note3
CSI01 (input)
INTP9/P80
transmission
/reception
1 0 1 1 × × × × × Master SCK01 SI01 KR7/ SI00/
Note3 Note3 Note3 Note3 _{CSI01 (output)}
P77 INTP9/P80
reception
0 0 1 × × 0 1 × × Master SCK01 KR6/P76 SO01 SI00/
Note3 Note3
Note3 Note3 _{CSI01 (output)}
INTP9/P80
transmission
1 0 1 1 × 0 1 × × Master SCK01 SI01 SO01 SI00/
Note3 Note3
CSI01 (output)
INTP9/P80
transmission
/reception
1×× × ×××1
Note3 Note3 Note3 Note3 Note3 Note3
× UART0 KR5/ KR6/P76 KR7/
reception P75
Note5, 6
P77
RxD0
Notes 1. The SE0 register is a read-only status register which is set using the SS0 and ST0 registers.
2. When channel 1 of unit 0 is set to UART0 reception, this pin becomes an RxD0 function pin. In this case, set
channel 0 of unit 0 to operation stop mode or UART0 transmission (refer to Table 14-5).
When channel 0 of unit 0 is set to CSI00, this pin cannot be used as an RxD0 function pin. In this case, set
channel 1 of unit 0 to operation stop mode or CSI01.
3. This pin can be set as a port function pin.
4. This is 0 or 1, depending on the communication operation. For details, refer to 14.3 (12) Serial output register
m (SOm).
5. When using UART0 transmission and reception in a pair, set channel 0 of unit 0 to UART0 transmission (refer to
Table 14-5).
6. The SMR00 register of channel 0 of unit 0 must also be set during UART0 reception. For details, refer to 14.5.2
(1) Register setting.
Remarks 1. X: Don’t care
2. For 78K0R/LF3, the channel 1 of unit 0 is not mounted.
3. For 78K0R/LG3, CSI01 is not mounted.
R01UH0004EJ0501 Rev.5.01
572
Jun 20, 2011