UPD78F1502AGK-GAK-AX Datasheet, PDF (470/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 14 SERIAL ARRAY UNIT
(5) Higher 7 bits of the serial data register mn (SDRmn)
SDRmn is the transmit/receive data register (16 bits) of channel n. Bits 7 to 0 function as a transmit/receive buffer
register, and bits 15 to 9 are used as a register that sets the division ratio of the operation clock (MCK).
If the CCSmn bit of serial mode register mn (SMRmn) is cleared to 0, the clock set by dividing the operating clock
by the higher 7 bits of SDRmn is used as the transfer clock.
For the function of the lower 8 bits of SDRmn, see 14.2 Configuration of Serial Array Unit.
SDRmn can be read or written in 16-bit units.
However, the higher 7 bits can be written or read only when the operation is stopped (SEmn = 0). During operation
(SEmn = 1), a value is written only to the lower 8 bits of SDRmn. When SDRmn is read during operation, 0 is
always read.
Reset signal generation clears this register to 0000H.
Figure 14-8. Format of Serial Data Register mn (SDRmn)
Address: FFF10H, FFF11H (SDR00), FFF12H, FFF13H (SDR01),
FFF44H, FFF45H (SDR02), FFF46H, FFF47H (SDR03),
FFF48H, FFF49H (SDR10), FFF4AH, FFF4BH (SDR11),
FFF14H, FFF15H (SDR12), FFF16H, FFF17H (SDR13)
FFF11H (SDR00)
After reset: 0000H
R/W
FFF10H (SDR00)
Symbol
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
SDRmn
0
SDRmn[15:9]
Transfer clock setting by dividing the operating clock (MCK)
0
0
0
0
0
0
0
0
0
0
0
0
0
1
MCK/2
MCK/4
0
0
0
0
0
1
0
MCK/6
0
0
0
0
0
1
1
MCK/8
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
1
1
1
1
1
1
0
•
•
•
MCK/254
1
1
1
1
1
1
1
MCK/256
Cautions 1. Be sure to clear bit 8 to “0”.
2. Setting SDRmn[15:9] = (0000000B, 0000001B) is prohibited when UART is used.
3. Setting SDRmn[15:9] = 0000000B is prohibited when the simplified I²C is used. Set
SDRmn[15:9] to 0000001B or greater.
Remarks 1. For the function of the lower 8 bits of SDRmn, see 14.2 Configuration of Serial Array Unit.
2. m: Unit number (m = 0, 1)
n: Channel number (n = 0 to 3)
R01UH0004EJ0501 Rev.5.01
454
Jun 20, 2011