UPD78F1502AGK-GAK-AX Datasheet, PDF (754/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 18 DMA CONTROLLER
18.6 Cautions on Using DMA Controller
(1) Priority of DMA
During DMA transfer, a request from the other DMA channel is held pending even if generated. The pending
DMA transfer is started after the ongoing DMA transfer is completed. If two DMA requests are generated at the
same time, however, DMA channel 0 takes priority over DMA channel 1.
If a DMA request and an interrupt request are generated at the same time, the DMA transfer takes precedence,
and then interrupt servicing is executed.
(2) DMA response time
The response time of DMA transfer is as follows.
Response time
Table 17-2. Response Time of DMA Transfer
Minimum Time
3 clocks
Maximum Time
10 clocks^Note
Note The maximum time necessary to execute an instruction from internal RAM is 16 clock cycles.
Cautions 1. The above response time does not include the two clock cycles required for a DMA
transfer.
2. When executing a DMA pending instruction (see 18.6 (4)), the maximum response
time is extended by the execution time of that instruction to be held pending.
3. Do not specify successive transfer triggers for a channel within a period equal to the
maximum response time plus one clock cycle, because they might be ignored.
Remark 1 clock: 1/fCLK (fCLK: CPU clock)
R01UH0004EJ0501 Rev.5.01
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Jun 20, 2011