HD6432351 Datasheet, PDF (984/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

Appendix F Timing of Transition to and Recovery from
Hardware Standby Mode
Timing of Transition to Hardware Standby Mode
(1) To retain RAM contents with the RAME bit set to 1 in SYSCR, drive the RES signal low at
least 10 states before the STBY signal goes low, as shown below. RES must remain low until
STBY signal goes low (delay from STBY low to RES high: 0 ns or more).
STBY
RES
t₁≥10t_cyc
t₂≥0ns
Figure F-1 Timing of Transition to Hardware Standby Mode
(2) To retain RAM contents with the RAME bit cleared to 0 in SYSCR, or when RAM contents do
not need to be retained, RES does not have to be driven low as in (1).
Timing of Recovery from Hardware Standby Mode
Drive the RES signal low and the NMI signal high approximately 100 ns or more before STBY
goes high to execute a power-on reset.
STBY
RES
NMI
t≥100ns
t_OSC
t_NMIRH
Figure F-2 Timing of Recovery from Hardware Standby Mode
964