HD6432351 Datasheet, PDF (496/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

TCFV Flag/TCFU Flag Setting Timing: Figure 10-44 shows the timing for setting of the TCFV
flag in TSR by overflow occurrence, and TCIV interrupt request signal timing.
Figure 10-45 shows the timing for setting of the TCFU flag in TSR by underflow occurrence, and
TCIU interrupt request signal timing.
ø
TCNT input
clock
TCNT
(overflow)
Overflow
signal
TCFV flag
TCIV interrupt
H'FFFF
H'0000
Figure 10-44 TCIV Interrupt Setting Timing
ø
TCNT
input clock
TCNT
(underflow)
Underflow signal
H'0000
H'FFFF
TCFU flag
TCIU interrupt
Figure 10-45 TCIU Interrupt Setting Timing
476