HD6432351 Datasheet, PDF (492/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

Timing for Counter Clearing by Compare Match/Input Capture: Figure 10-38 shows the
timing when counter clearing by compare match occurrence is specified, and figure 10-39 shows
the timing when counter clearing by input capture occurrence is specified.
ø
Compare
match signal
Counter
clear signal
TCNT
N
TGR
N
H'0000
Figure 10-38 Counter Clear Timing (Compare Match)
ø
Input capture
signal
Counter clear
signal
TCNT
N
TGR
H'0000
N
Figure 10-39 Counter Clear Timing (Input Capture)
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