HD6432351 Datasheet, PDF (776/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

Table A-5 Number of Cycles in Instruction Execution
Instruction
ADD
ADDS
ADDX
AND
ANDC
BAND
Bcc
Mnemonic
ADD.B #xx:8,Rd
ADD.B Rs,Rd
ADD.W #xx:16,Rd
ADD.W Rs,Rd
ADD.L #xx:32,ERd
ADD.L ERs,ERd
ADDS #1/2/4,ERd
ADDX #xx:8,Rd
ADDX Rs,Rd
AND.B #xx:8,Rd
AND.B Rs,Rd
AND.W #xx:16,Rd
AND.W Rs,Rd
AND.L #xx:32,ERd
AND.L ERs,ERd
ANDC #xx:8,CCR
ANDC #xx:8,EXR
BAND #xx:3,Rd
BAND #xx:3,@ERd
BAND #xx:3,@aa:8
BAND #xx:3,@aa:16
BAND #xx:3,@aa:32
BRA d:8 (BT d:8)
BRN d:8 (BF d:8)
BHI d:8
BLS d:8
BCC d:8 (BHS d:8)
BCS d:8 (BLO d:8)
BNE d:8
BEQ d:8
BVC d:8
BVS d:8
BPL d:8
BMI d:8
BGE d:8
BLT d:8
BGT d:8
BLE d:8
BRA d:16 (BT d:16)
BRN d:16 (BF d:16)
Instruction
Fetch
I
1
1
2
1
3
1
1
1
1
1
1
2
1
3
2
1
2
1
2
2
3
4
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
Branch
Address
Read
J
Stack
Operation
K
Byte Data
Access
L
Word Data
Access
M
Internal
Operation
N
1
1
1
1
1
1
756