HD6432351 Datasheet, PDF (924/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

TIER1—Timer Interrupt Enable Register 1
H'FFE4
TPU1
Bit
:
Initial value :
Read/Write :
7
TTGE
0
R/W
6
5
4
3
— TCIEU TCIEV —
1
0
0
0
—
R/W R/W
—
2
1
0
— TGIEB TGIEA
0
0
0
—
R/W R/W
TGR Interrupt Enable A
0 Interrupt requests (TGIA)
by TGFA bit disabled
1 Interrupt requests (TGIA)
by TGFA bit enabled
TGR Interrupt Enable B
0 Interrupt requests (TGIB)
by TGFB bit disabled
1 Interrupt requests (TGIB)
by TGFB bit enabled
Overflow Interrupt Enable
0 Interrupt requests (TCIV) by TCFV disabled
1 Interrupt requests (TCIV) by TCFV enabled
Underflow Interrupt Enable
0 Interrupt requests (TCIU) by TCFU disabled
1 Interrupt requests (TCIU) by TCFU enabled
A/D Conversion Start Request Enable
0 A/D conversion start request generation disabled
1 A/D conversion start request generation enabled
904