HD6432351 Datasheet, PDF (585/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

Figure 13-6 shows an example of the operation for transmission in asynchronous mode.
Start
1 bit
Data
Parity Stop Start
bit bit bit
Data
Parity Stop
bit bit
1
0 D0 D1
D7 0/1 1 0 D0 D1
D7 0/1
1
Idle state
(mark state)
TDRE
TEND
TXI interrupt
Data written to TDR and
request generated TDRE flag cleared to 0 in
TXI interrupt service routine
TXI interrupt
request generated
TEI interrupt
request generated
1 frame
Figure 13-6 Example of Operation in Transmission in Asynchronous Mode
(Example with 8-Bit Data, Parity, One Stop Bit)
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