HD6432351 Datasheet, PDF (708/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

21.3.2 Control Signal Timing
Table 21-5 lists the control signal timing.
Table 21-5 Control Signal Timing—
Condition A: V_CC = 2.7 to 5.5 V, AV_CC = 2.7 to 5.5 V, V_ref = 2.7 V to AV_CC,
V_SS = AV_SS = 0 V, ø = 2 to 10 MHz, T_a = –20 to +75°C (regular specifications),
T_a = –40 to +85°C (wide-range specifications)
Condition B: V_CC = 5.0 V ± 10%, AV_CC = 5.0 V ± 10%, V_ref = 4.5 V to AV_CC,
V_SS = AV_SS = 0 V, ø = 2 to 20 MHz, T_a = –20 to +75°C (regular specifications),
T_a = –40 to +85°C (wide-range specifications)
Item
RES setup time
RES pulse width
NMI reset setup time
NMI reset hold time
NMI setup time
NMI hold time
NMI pulse width (exiting
software standby mode)
IRQ setup time
IRQ hold time
IRQ pulse width (exiting
software standby mode)
Condition A Condition B
Symbol Min Max Min Max Unit
t _RESS
200 — 200 — ns
t _RESW
20
—
20
—
t _cyc
t _NMIRS
250 —
200 —
ns
t _NMIRH
200 —
200 —
t _NMIS
250 — 150 — ns
t _NMIH
10 — 10 —
t _NMIW
200 — 200 — ns
Test Conditions
Figure 21-6
Figure 21-7
t _IRQS
t _IRQH
t _IRQW
250 — 150 — ns
10 — 10 — ns
200 — 200 — ns
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