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HD6432351 Datasheet, PDF (306/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise | |||
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8.2 Register Descriptions
8.2.1 DTC Mode Register A (MRA)
MRA is an 8-bit register that controls the DTC operating mode.
Bit
:
Initial value :
R/W
:
7
SM1
Unde-
fined
â
6
SM0
Unde-
fined
â
5
DM1
Unde-
fined
â
4
DM0
Unde-
fined
â
3
MD1
Unde-
fined
â
2
MD0
Unde-
fined
â
1
DTS
Unde-
fined
â
0
Sz
Unde-
fined
â
Bits 7 and 6âSource Address Mode 1 and 0 (SM1, SM0): These bits specify whether SAR is
to be incremented, decremented, or left fixed after a data transfer.
Bit 7
SM1
0
1
Bit 6
SM0
â
0
1
Description
SAR is fixed
SAR is incremented after a transfer
(by +1 when Sz = 0; by +2 when Sz = 1)
SAR is decremented after a transfer
(by â1 when Sz = 0; by â2 when Sz = 1)
Bits 5 and 4âDestination Address Mode 1 and 0 (DM1, DM0): These bits specify whether
DAR is to be incremented, decremented, or left fixed after a data transfer.
Bit 5
DM1
0
1
Bit 4
DM0
â
0
1
Description
DAR is fixed
DAR is incremented after a transfer
(by +1 when Sz = 0; by +2 when Sz = 1)
DAR is decremented after a transfer
(by â1 when Sz = 0; by â2 when Sz = 1)
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