HD6432351 Datasheet, PDF (864/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

IER—IRQ Enable Register
H'FF2E
Interrupt Controller
Bit
:
Initial value :
Read/Write :
7
IRQ7E
0
R/W
6
IRQ6E
0
R/W
5
IRQ5E
0
R/W
4
IRQ4E
0
R/W
3
IRQ3E
0
R/W
2
IRQ2E
0
R/W
1
IRQ1E
0
R/W
0
IRQ0E
0
R/W
IRQn Enable
0 IRQn interrupt disabled
1 IRQn interrupt enabled
(n = 7 to 0)
ISR—IRQ Status Register
H'FF2F
Interrupt Controller
Bit
:
Initial value :
Read/Write :
7
IRQ7F
0
R/(W)*
6
IRQ6F
0
R/(W)*
5
IRQ5F
0
R/(W)*
4
IRQ4F
0
R/(W)*
3
IRQ3F
0
R/(W)*
2
IRQ2F
0
R/(W)*
1
IRQ1F
0
R/(W)*
0
IRQ0F
0
R/(W)*
Indicate the status of IRQ7 to IRQ0 interrupt requests
Note: * Can only be written with 0 for flag clearing.
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