HD6432351 Datasheet, PDF (494/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

10.6.2 Interrupt Signal Timing
TGF Flag Setting Timing in Case of Compare Match: Figure 10-42 shows the timing for
setting of the TGF flag in TSR by compare match occurrence, and TGI interrupt request signal
timing.
ø
TCNT input
clock
TCNT
N
N+1
TGR
N
Compare
match signal
TGF flag
TGI interrupt
Figure 10-42 TGI Interrupt Timing (Compare Match)
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