HD6432351 Datasheet, PDF (326/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

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DTC activation
request
DTC
request
Address
Vector read
Data transfer
Read Write
Data transfer
Read Write
Transfer
information
read
Transfer Transfer
information information
write
read
Transfer
information
write
Figure 8-12 DTC Operation Timing (Example of Chain Transfer)
8.3.10 Number of DTC Execution States
Table 8-8 lists execution statuses for a single DTC data transfer, and table 8-9 shows the number
of states required for each execution status.
Table 8-8 DTC Execution Statuses
Mode
Normal
Repeat
Block transfer
Vector Read
I
1
1
1
Register Information
Internal
Read/Write
Data Read Data Write Operations
J
K
L
M
6
1
1
3
6
1
1
3
6
N
N
3
N: Block size (initial setting of CRAH and CRAL)
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