HD6432351 Datasheet, PDF (504/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

Contention between TGR Write and Input Capture: If the input capture signal is generated in
the T2 state of a TGR write cycle, the input capture operation takes precedence and the write to
TGR is not performed.
Figure 10-54 shows the timing in this case.
ø
Address
Write signal
Input capture
signal
TCNT
TGR
TGR write cycle
T1
T2
TGR address
M
M
Figure 10-54 Contention between TGR Write and Input Capture
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